The present invention relates generally to the field of data processing within a computing environment, and more particularly to ordered stores in a non-uniform memory subsystem at sufficient bandwidth to satisfy Peripheral Component Interconnect Express (PCIe) specifications.
A CPU cache is a cache used by the central processing unit (CPU) of a computer to reduce the average time to access data from system memory. The cache is a memory, smaller and faster than system memory. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of cache levels (L1, L2, L3, etc.)
PCIe, is a serial computer expansion bus standard designed to replace the older PCI (Peripheral Component Interconnect), PCI-X (Peripheral Component Interconnect eXtended), and AGP (Accelerated Graphics Port) bus standards.
Data originating from, for example, a hard drive I/O adapter, en route to system memory, may pass from a PCI Bridge Controller (PBC) to Level 3 cache (L3), or another cache level such as level 4 cache. The data may comprise a series of data packets, and the data packets must be stored, in L3 cache, in the proper order to avoid data corruption.